Taiwan Semiconductor Manufacturing (TSMC) is keeping microbumps for advanced packaging that connects high-bandwidth memory (HBM) to AI accelerators, while asking materials and equipment partners to develop 5-micrometer (μm)-class bumps and compatible underfill materials. Industry sources said on September 2 that South Korean and Japanese suppliers had started development, with mass production estimated for the second half of 2027. Current bump heights are 15–25μm for HBM3E and approximately 10μm for HBM4. Hybrid bonding, which directly connects copper pads without bumps, is expected to become feasible only after late fourth-generation or early fifth-generation HBM. TSMC continues using microbumps in its CoWoS (chip-on-wafer-on-substrate) packaging because the method has established yield, inspection and mass-production performance, although the 5μm target requires simultaneous control of void-free underfill, residual flux and alignment. JEDEC (Joint Electron Device Engineering Council) limits HBM cube height to 775μm, requiring denser, lower connections as input/output counts rise. SK Hynix and Samsung Electronics use MR-MUF and TC-NCF underfill approaches, respectively, while SK Hynix’s roadmap keeps MR-MUF through HBM4 and HBM4E and defers direct bonding to HBM5 and stacks above 20 layers. The broader HBM market is also moving toward custom memory and tighter logic integration as inference workloads increase data movement. SK Hynix said custom HBM4 could improve large language model inference performance by up to 5.15 times, while future 3D structures could reduce data-transfer energy from 2–3 picojoules per bit to 0.2–0.3 pJ. CXMT has reportedly started small-volume HBM3E production, but industry estimates put it three to five years behind leading suppliers. TSMC’s approach may support near-term supply stability while delaying some longer-term performance gains from hybrid bonding, increasing the importance of cooperation across materials, equipment, memory and foundry companies.