Samsung Electronics has detailed the development strategy for its V10 BV-NAND, a next-generation V-NAND (vertically stacked NAND flash memory) device with more than 400 layers. Rather than simply increasing the layer count, Samsung divided memory cells into three independently manufactured stacks and connected them vertically through a 3-stack HARC merge approach. Combined with multi-hole and zero dummy-hole technologies, the design delivered a 58% improvement in bit density, a 33% improvement in I/O speed and a 25% reduction in power consumption. The V10 also supports I/O speeds of 4.8 Gbps or higher, 128-terabyte-class SSDs and next-generation PCIe 7.0 SSDs. Samsung introduced the technology through its semiconductor newsroom on the 31st, after the V10 received the 3D NAND Innovation Award at Flash Memory Summit 2026 in the United States earlier this month. Wafer bonding (joining separately fabricated wafers vertically) separates the cell array from peripheral circuitry, helping improve circuit performance and reduce chip size. Samsung also cut voltage applied to unselected stacks during writing by more than 70% and improved the bit error rate by 4%. The company is targeting AI data-center storage, where rising data and bandwidth demands have made power consumption an important component of total cost of ownership. Samsung said the wafer-bonding and three-stack technologies could provide a foundation for V-NAND with more than 500 layers in the future.