TSMC validates A16 process with backside power delivery, targets Q4 2026 production

TSMC has completed development and technical validation of its A16 semiconductor process and is expected to begin mass production in the fourth quarter of 2026. The 1.6-nanometer-class CMOS platform is the company's first angstrom-class process to feature Super Power Rail, or SPR, a backside power-delivery architecture that separates signal routing from power routing to ease wiring bottlenecks. Reports comparing A16 with TSMC's 2-nanometer process cite 8% to 10% higher computing speed, 15% to 20% lower energy consumption and an 8% to 10% increase in chip density. Earlier TSMC comparisons with its enhanced N2P process used the same ranges and specified the gains at equivalent power or performance levels. A16 is positioned as a transitional technology toward TSMC's 1.4-nanometer A14 process, which is targeted for mass production in 2028, while the company is also expanding advanced-process and packaging capacity amid strong AI-chip demand and CoWoS constraints.

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