The widening gap between AI compute performance and memory bandwidth is becoming a structural constraint on accelerator performance, Micron Fellow Raghu Sriramaneni said at Hot Chips 2026. AI accelerator compute is rising roughly threefold every two years, while HBM bandwidth is growing by less than twofold, leaving data-intensive workloads vulnerable to underused compute capacity. Micron also cited Meta's Llama 3 data showing that HBM failures accounted for about 17% of unexpected training interruptions. New package designs integrating two GPUs with eight 12-high HBM4 stacks put memory at about 90% of semiconductor area, more than eight times the GPU area, while equivalent HBM capacity requires about three times the wafer area of standard DDR5 DRAM. Micron is pursuing SerDes and die-to-die PHYs optimized for memory, larger system-in-package designs, glass substrates, liquid cooling, hybrid bonding and fusion bonding to address bandwidth, heat, reliability and manufacturing constraints.