ETNews said TSMC is lining up materials, components and equipment suppliers for panel-level packaging and discussing MCE equipment investments ahead of a pilot line this year and possible mass production next year.
TSMC is building a supply chain for CoPoS materials, components and equipment and is discussing equipment investments with MCE companies as it pushes toward panel-level packaging mass production as early as next year, ETNews reported on June 15. The company plans to run a pilot line this year before moving into PLP, a packaging approach that places diced chips on rectangular panels instead of circular wafers. The format can reduce edge waste versus wafer-level packaging and, using a standard 600×600 millimeter panel, is estimated to deliver roughly 5 to 6 times the chip output of a mainstream 300 millimeter, 12-inch wafer. The move would sharpen competition with Samsung in advanced packaging for AI and HPC chips.