TSMC develops CoPoS AI chip packaging technology to challenge Intel EMIB

TSMC is developing an EMIB-like advanced chip-packaging technology in collaboration with Kinsus Interconnect Technology Corp., The Information reported, adding a new track to the Taiwanese chipmaker’s effort to ease AI packaging bottlenecks and compete more directly with Intel’s Embedded Multi-die Interconnect Bridge. The development broadens TSMC’s packaging roadmap beyond its previously reported CoPoS, or Chip-on-Panel-on-Substrate, program, which is aimed at expanding usable manufacturing area and relieving pressure on constrained CoWoS capacity. The new bridge-based approach highlights how competition in AI semiconductors is shifting from leading-edge process nodes to packaging, where multiple silicon dies are assembled into a single high-performance system. Intel’s EMIB differs from TSMC’s mainstream CoWoS approach by using small embedded silicon bridges only where chiplets need to communicate, rather than a large interposer spanning the full package. Industry observers cited in the report suggest TSMC’s project may seek to eliminate the redistribution-layer interposer used in CoWoS-L and move closer to Intel’s lower-material, potentially less complex architecture. The move comes as demand for advanced AI packaging continues to outstrip supply. Nomura Securities estimates TSMC’s CoWoS capacity will reach 2 million wafers by 2027, with Nvidia expected to consume about 55% of that output, while some CoWoS-L lead times have stretched to 78 weeks and capacity is reported sold out through 2026 and well into 2027. TSMC has also announced a CoWoS glass substrate program and is building a CoPoS pilot line in Tainan, Taiwan, with volume production expected in the second half of 2028. TSMC’s U.S.-listed shares rose 7.6% on Thursday, while Intel gained roughly 13%.