The FMS 2026 showcase pairs Switchtec Gen 6 PCIe switches with Micron’s mass-produced PCIe Gen 6 SSDs to validate full-speed throughput across multiple drives for AI, cloud and HPC infrastructure.
Microchip Technology and Micron Technology jointly demonstrated an end-to-end PCIe Gen 6 storage architecture at the Future of Memory and Storage Conference on Aug. 4, 2026, combining Microchip’s Switchtec Gen 6 PCIe fanout switches with Micron’s 9650 NVMe SSDs. The demonstration is designed to show that multiple SSDs can run simultaneously at full Gen 6 speeds rather than sharing a constrained bus, a point that matters for AI, cloud and high-performance computing systems that need higher sustained data movement across compute, memory and storage. PCIe Gen 6 doubles PCIe Gen 5 bandwidth to 64 gigatransfers per second per lane. Micron’s 9650, described as the first PCIe Gen 6 data center SSD to reach mass production, delivers sequential read speeds of up to about 28 GB/s. Microchip said its Switchtec Gen 6 switches support up to 160 lanes and are built on a 3 nm process, while also including hardware root of trust, advanced error containment, multicast support and post-quantum-safe cryptography aligned with CNSA 2.0. The companies positioned the demonstration as an end-to-end validation of storage and switching hardware operating together at full throughput, which can reduce integration risk for data center operators. Brian McCarson said storage and switching technologies need to be designed cohesively, while Larry Hart linked the architecture to rising AI infrastructure demands. For investors watching Microchip and Micron, the demo underscores Micron’s early position in Gen 6 SSD deployment and highlights security and system-level features that could matter as cloud and regulated buyers evaluate next-generation infrastructure.